1. Technical Field
The invention relates to a method of fabricating an electrode on a semiconductor substrate. In particular, the invention concerns fabrication of a vertically profiled electrode like a T-gate or a Γ-gate. The invention further relates to a semiconductor device comprising such a vertically profiled electrode.
2. Description of the Prior Art
The rapid progress in material growth and device fabrication has greatly improved the performance of semiconductor devices like heterostructure field effect transistors in recent years. Such semiconductor devices were conventionally provided with gate electrodes having a triangular cross section. However, scaling down of the profile geometry of triangular-shaped gate electrodes with the intention to achieve shorter electron transit times leads to a strong increase of the gate end-to-end resistance. This not only deteriorates the high-frequency performance of the semiconductor device but also its power-gain cutoff frequency and its noise behavior.
In order to solve the problems associated with triangular-shaped gate electrodes, vertically profiled gate electrodes like T- or Γ-shaped gate electrodes (T- or Γ-gates) have been proposed. Vertically profiled gate electrodes in the form of T- or Γ-gates combine small footprints, i.e., short gate lengths, with large cross-sectional areas.
Fabrication methods and fabrication limits of T- or Γ-gates are exemplarily discussed in B. E. Maile “Fabrication limits of nanometer T- and Γ-gates: Theory and Experiment”, J. Vac. Sci. Technol. B 11(6), November/December 1993, pages 2502 to 2508. In this article fabrication of T- and Γ-gates in the sub-100 nm regime using electron beam lithography, multi-layer resist stacks and lift-off is described.
During fabrication of the T- and Γ-gates a bilayer resist stack is arranged on the semiconductor substrate. The bilayer resist stack is exposed by way of electron beam lithography and then developed in order to locally open and vertically as well as horizontally pattern the resist stack. After the resist stack has been patterned, a gate metal is deposited on the patterned resist stack and a lift-off is performed to remove the patterned resist stack together with the gate metal deposited thereon.
The bilayer resist stack consists of a first resist layer (bottom resist) arranged on the semiconductor substrate and a second resist layer (top resist) arranged on the bottom resist. Both resist layers are formed from positive electron resists. In a positive electron resist, electron-polymer interaction taking place during exposure by the impinging electrons causes chemical bonds to be broken (chain scission) to form shorter molecular fragments. As a result, the molecular weight is reduced in the irradiated areas. The irradiated areas are later dissolved in a developer that attacks the low-molecular-weight material.
The T- and Γ-gate fabrication described above requires an electron dose profile as depicted in FIG. 1a. As can be seen from FIG. 1a, the electron dose profile consists of a quasi-line exposure 10 and an overlaid area exposure 12. The quasi-line exposure 10 defines the length of the gate in an x-direction and is also referred to as “core” exposure, whereas the overlaid area or “frame” exposure 12 defines the gate head. Changes of cross-sectional geometry, i.e., T- and Γ-shape, can easily be realized by changing the relative x-position of core and frame exposure.
As can be seen from FIG. 1a, the electron dose D1 required to expose the bottom resist is higher than the electron dose D2 for top resist exposure. This means that the sensitivity, which is defined as the electron dose required per unit area to give complete development, of the top resist is higher than the sensitivity of the bottom resist. Different resist sensitivities are necessary to control the vertical profiling of the gate electrode.
There is a need for a method of fabricating a vertically profiled electrode on a semiconductor substrate which allows a better control of the vertical electrode profile. There is also a need for a semiconductor device having such a vertically profiled electrode.